notesonly.in

One notebook for every subject — open it anywhere.

Log in

ARM Cortex Basics: Complete Beginner's Guide For students.

EngineeringTry the interactive 3D model →

ARM Cortex is the processor family inside nearly every smartphone, smartwatch and fitness band on the planet. ARM manufactures nothing — it licenses processor designs that STMicroelectronics, Nordic, NXP and others build into chips. The Cortex name covers three profiles for different jobs, all sharing an efficient 32-bit RISC foundation.

Cortex is the default processor to learn in embedded engineering: one architecture spans 50-cent sensor nodes (Cortex-M0+), motor controllers (Cortex-M4/M7), car safety systems (Cortex-R) and phone processors (Cortex-A). Learn the Cortex-M once and the whole industry opens up.

Key Concepts

  • Cortex-M (microcontroller): bare-metal or RTOS, no MMU. M0+/M3 for control; M4 adds DSP instructions and optional FPU; M7 adds caches.
  • Cortex-A (application): has an MMU, runs Linux/Android — the cores in phones and Raspberry Pi boards.
  • Cortex-R (real-time): hard-real-time safety systems (braking, storage controllers) with tightly-coupled memory and lockstep cores.
  • Thumb-2: mixes 16-bit and 32-bit instructions for dense code with near-32-bit performance.
  • NVIC: the Nested Vectored Interrupt Controller stacks registers in hardware, supports priorities and tail-chaining — tiny, deterministic interrupt latency.
  • Registers: R0–R15 (R13 = stack pointer, R14 = link register, R15 = PC), plus MSP/PSP stack pointers and the xPSR status register.

How It Works

A Cortex-M runs a short pipeline — typically fetch, decode, execute — so throughput nears one instruction per clock. Its load-store architecture touches memory only via load/store instructions; arithmetic happens between registers. On reset, the core reads flash word 0 as the stack pointer and word 1 as the reset vector. Interrupts use a vector table of handler addresses; the NVIC auto-stacks eight registers on entry (~12 cycles on M3), so plain C functions can serve interrupts. Sleep modes gate clocks while RAM and NVIC stay alive — why a sensor node runs years on a coin cell.

Worked Example

Build a 1 ms system tick on a 48 MHz Cortex-M with SysTick. Step 1: RELOAD = (clock × period) − 1. Step 2: 48,000,000 × 0.001 − 1 = 47,999 = 0xBB7F. Step 3: the reload register is 24-bit (max 16,777,215) — fits easily. Step 4: write 47999 to LOAD, clear VAL, set ENABLE + TICKINT + CLKSOURCE in CTRL. Result: SysTick_Handler fires exactly every 1 ms — the heartbeat an RTOS uses for delays and scheduling. At 10 ms the reload would be 479,999, still in range.

Common Misconceptions

  • "ARM makes chips." ARM is an IP licensor; your STM32 was made by STMicroelectronics around an ARM core.
  • "Cortex-M runs Linux." Linux needs an MMU, which Cortex-M lacks — Linux-class work belongs to Cortex-A; M runs bare-metal or an RTOS.
  • "Higher MHz always wins." A Cortex-M0+ delivers ~0.95 DMIPS/MHz at microamps per MHz — for battery devices, performance per watt beats raw clock.

Real-World Applications

  • STM32: the most popular Cortex-M line — 3D printers, drones, industrial drives.
  • Bluetooth LE: Nordic nRF52/nRF53 (Cortex-M4) in earbuds, beacons, wearables.
  • Phones: Cortex-A cores run Android/iOS application software.
  • Car safety: Cortex-R cores handle braking and airbags with lockstep redundancy.

Cortex wins through specialization — M for microcontrollers, A for applications, R for real time — on one efficient RISC philosophy. Grasp the pipeline, the NVIC and SysTick math, and any Cortex-M datasheet becomes approachable.

Related blogs