Low-power design techniques basics
VLSI Design · Engineering
Study notes
Phone: clock gating stops unused blocks; DVFS lowers V/f when idle; power gating cuts leakage (sleep). Battery life from these. Design for power.
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VLSI Design · Engineering
Phone: clock gating stops unused blocks; DVFS lowers V/f when idle; power gating cuts leakage (sleep). Battery life from these. Design for power.