notesonly.in

One notebook for every subject — open it anywhere.

Log in

Combinational Circuits: Multiplexers, Decoders and Encoders

EngineeringTry the interactive 3D model →

A combinational circuit is logic without memory: outputs depend only on present inputs. Multiplexers route one of many inputs to one output, demultiplexers reverse it, decoders translate a binary code into one active line among many, and encoders compress many lines back into binary. These four are the traffic controllers of digital systems.

Data must be steered: ALU operation selection uses a multiplexer, memory chips are picked from the address bus by a decoder, keyboards encode presses into binary, seven-segment displays decode binary into digits. Wherever bits need routing or translating, these circuits work.

Key Concepts

  • Multiplexer: 2^n data inputs, n select lines, one output. A 4:1 MUX has 4 inputs, 2 selects.
  • 4:1 MUX equation: Y = S1'.S0'.D0 + S1'.S0.D1 + S1.S0'.D2 + S1.S0.D3; one term active per select code.
  • Demultiplexer: One input routed to one of 2^n outputs; the rest stay idle.
  • Decoder: n inputs activate one of 2^n outputs. A 3:8 decoder (74138) turns 3 bits into 8 lines; enable inputs let chips combine into bigger decoders.
  • Encoder: The inverse: 2^n inputs to an n-bit code. A priority encoder (74148) honors the highest active input.
  • BCD to seven-segment: Translates a 4-bit digit into segment signals a-g; the 7447/7448 are classics.
  • Combinational test: No flip-flops, no clock. Same inputs always give same outputs.

How It Works

  1. 4:1 MUX anatomy: Four AND gates each pair one data input with one select pattern (S1'.S0' for D0 … S1.S0 for D3); an OR merges them.
  2. Select D2: S1=1, S0=0 leaves only S1.S0' alive, so Y = D2.
  3. Decoder as address selector: A 3-bit address into a 3:8 decoder activates exactly one of 8 outputs, enabling one memory chip.
  4. The pattern: MUX selects among data with a code; decoder expands a code to one-hot lines; encoder compresses one-hot back to a code.

Worked Example

4:1 MUX with D0=1, D1=0, D2=1, D3=0, S1=1, S0=0. Step 1: select code 10 activates S1.S0'.D2. Step 2: evaluate terms: S1'.S0'.D0 = 0, S1'.S0.D1 = 0, S1.S0'.D2 = 1, S1.S0.D3 = 0. Step 3: Y = 0+0+1+0 = 1, exactly D2. Bonus: an 8:1 MUX needs n with 2^n = 8, so 3 select lines.

Common Misconceptions

  • "A MUX mixes inputs." It selects exactly one; the rest are ignored. Rotary switch, not mixer.
  • "Decoder and encoder are the same." Inverses: decoder expands n bits to 2^n lines; encoder compresses back.
  • "DEMUX equals decoder." A DEMUX routes a data signal to the selected output; a decoder merely activates a line. A decoder with data on its enable pin becomes a DEMUX.

Real-World Applications

  • Processors: MUXes select ALU operations and register sources every cycle.
  • Memory: Address decoders choose which chip answers; this is how memory maps work.
  • Displays: BCD-to-seven-segment decoders drive clocks and meters.
  • Inputs/comms: Keyboard encoders; time-division multiplexing shares wires among signals.

Combinational circuits route and translate without remembering: multiplexers select one input by code, demultiplexers fan one input out, decoders expand n bits to 2^n lines, encoders compress back. The example shows the mechanism: select 10 activates only S1.S0'.D2, so Y = D2. Keep the family straight and these four blocks will recur in every digital system you study.

Related blogs