Sequential Circuits: Flip-Flops and Latches For students.

A sequential circuit has memory: outputs depend on present inputs plus past history. The memory bit lives in a latch or flip-flop, holding one bit until told to change. With a clock, flip-flops become registers, counters, shift registers and the state machines that run processors.

Combinational logic forgets instantly; without memory there are no variables, programs or counting. The gap between a calculator and a computer is sequential logic: flip-flops holding state, updated billions of times per second.

Key Concepts

• Latch vs flip-flop: Latch is level-sensitive (transparent while enabled); flip-flop is edge-triggered (samples at the clock edge). Flip-flops rule synchronous design.
• SR latch: Cross-coupled gates; S=1 sets, R=1 resets, S=R=0 holds, S=R=1 is forbidden.
• D latch: Output follows D while enabled, freezes when disabled; transparent, not edge-triggered.
• D flip-flop: On each active edge Q becomes D (Q+ = D). The register workhorse.
• JK flip-flop: Q+ = J.Q' + K'.Q. 00 holds, 10 sets, 01 resets, 11 toggles, ideal for counters.
• T flip-flop: Toggles when T=1; a JK with J=K=T.
• Characteristic vs excitation: Next state from inputs, versus inputs needed for a desired transition (used in counter design).
• Race-around: Level-triggered JK with J=K=1 can toggle repeatedly in one pulse; edge triggering killed this historical bug.
• Setup/hold: Data must be stable before and after the clock edge; violations risk metastability.
• Propagation delay: Q updates nanoseconds after the edge, never instantly.

How It Works

1. Storing a bit: Cross-coupled gates feed outputs back as inputs, making two stable states; an S or R pulse flips the loop.
2. Clocking: An edge-triggered D flip-flop copies D to Q only at the clock edge: clean synchronous behavior.
3. Toggling: JK with J=K=1 inverts Q every rising edge: a divide-by-2 stage.
4. Register: Four D flip-flops on one clock snapshot a nibble every cycle.
5. Timing discipline: Hold data stable through the setup-hold window and the system marches in lockstep.

Worked Example

JK flip-flop, J=K=1, starting Q=0, three rising edges. Edge 1: toggle, Q = 1. Edge 2: toggle, Q = 0. Edge 3: toggle, Q = 1. Output sequence 1,0,1: a perfect clock divide-by-2. Contrast a D flip-flop with D=1: every edge forces Q=1, so after the first edge Q stays 1 forever. Same clock, same start, different behavior, decided entirely by type and input equations.

Common Misconceptions

• "Latch = flip-flop." Latch is level-sensitive; flip-flop edge-triggered. Swapping breaks synchronous timing.
• "S=R=1 stores the bit." It is the forbidden state: both outputs forced equal, settling unpredictably on release.
• "Output changes exactly at the edge." Propagation delay adds nanoseconds; at high clock rates those are the whole timing budget.

Real-World Applications

• Registers/RAM: CPU registers, pipelines and SRAM cells are latch/flip-flop arrays.
• Counters: Toggling flip-flops count events and divide clocks, watches to synthesizers.
• State machines: Protocol controllers and CPU control units: flip-flop state plus next-state logic.
• Synchronizers: Flip-flop chains bring pushbuttons safely into the clock domain.

Sequential circuits remember: latches hold while enabled, flip-flops capture at the edge; SR, D, JK and T each have their equation, Q+ = D and Q+ = J.Q' + K'.Q being the famous two. The trace shows J=K=1 toggling Q through 1,0,1. Honor setup and hold, never assert S=R=1, and one-bit memories scale into registers, counters and processors.