MOSFET and JFET Operation Characteristics For students.

A MOSFET and a JFET are the two families of field-effect transistors. In both, the gate voltage creates an electric field that widens or narrows the channel between drain and source, controlling the current. Unlike a bipolar transistor, which needs base current, the FET gate draws practically no DC current, giving extremely high input impedance.

MOSFETs are the switches inside every processor and memory chip, billions per chip. JFETs are the quiet specialists in microphone preamps and radio front ends. How each behaves is the foundation of analog and digital design.

Key Concepts

• Terminals: Gate (G), Drain (D), Source (S). Current flows drain-to-source through the channel; gate voltage controls its width. n-channel uses electrons; p-channel holes with reversed polarities.
• JFET: The gate forms a pn junction with the channel and must stay reverse-biased, so only tiny leakage flows.
• Pinch-off voltage (Vp): The negative (n-channel) gate voltage at which depletion regions close the channel and drain current falls to nearly zero. IDSS is the drain current at Vgs = 0.
• MOSFET gate: A thin silicon-dioxide layer insulates the gate, so DC gate current is essentially zero. Enhancement types are normally OFF and need Vgs beyond Vth (~1-3 V); depletion types are normally ON and turn off as the gate depletes the built-in channel.
• Regions: Cutoff (off), triode/ohmic (voltage-controlled resistor), saturation (constant current, used for amplification). Transconductance (gm), in siemens, is drain-current change per volt of gate change.

Formulas

• JFET Shockley equation (saturation): Id = IDSS x (1 - Vgs/Vp)^2; Vp is negative for n-channel.
• JFET transconductance: gm = (2 x IDSS / |Vp|) x (1 - Vgs/Vp), maximum at Vgs = 0, zero at pinch-off.
• MOSFET square law (long-channel saturation): Id = (k/2) x (Vgs - Vth)^2, k a device constant in A/V^2.
• Limits: Square-law assumes long channels and saturation. In nanometer MOSFETs, velocity saturation linearizes the curve and Vth drifts with temperature, so final designs use simulator models.

Worked Example

An n-channel JFET: IDSS = 8 mA, Vp = -4 V, Vgs = -1 V. Step 1: Vgs/Vp = 0.25. Step 2: 1 - 0.25 = 0.75. Step 3: 0.75^2 = 0.5625. Step 4: Id = 8 x 0.5625 = 4.5 mA. Transconductance: gm = (2 x 8/4) x 0.75 = 3 mS, so a 10 mV gate wiggle shifts drain current 30 microamps.

Common Misconceptions

• "The gate draws no current, so I can leave it floating." A floating MOSFET gate collects static and can switch randomly or be destroyed. Always tie it to a defined voltage.
• "Enhancement and depletion MOSFETs are interchangeable." Enhancement is OFF at zero gate volts; depletion is ON. Swapping inverts the circuit.
• "Pinch-off means the JFET is off." Vp is the turn-off voltage, but "pinch-off" also names the start of the saturation region, where the device is fully on.

Real-World Applications

• CMOS logic: Every CPU and memory chip uses complementary enhancement MOSFETs, drawing power only while switching.
• Power MOSFETs: Chargers, motor drivers and EVs switch tens of amps with low on-resistance.
• JFET preamps: Microphones, guitar pickups and instruments use JFET inputs for low noise and high impedance.
• Analog switches: MOSFETs route audio and video as near-perfect on/off switches.

MOSFETs and JFETs are both voltage-controlled transistors: the JFET squeezes a built-in channel with a reverse-biased pn junction, while the MOSFET builds its channel under an insulated gate drawing no DC current. Enhancement MOSFETs start OFF and turn on past Vth; JFETs and depletion MOSFETs start ON and turn off toward pinch-off. In saturation both follow square-law curves: a -1 V bias on an 8 mA, -4 V JFET gives 4.5 mA at 3 mS transconductance.