Semiconductor Fabrication Basics: Complete Beginner's Guide

Semiconductor fabrication turns a disc of ultra-pure silicon into a microchip by repeating a small set of steps, cleaning, layering, patterning, etching and doping, dozens or hundreds of times. Transistors, wires and insulation are built layer upon layer like a microscopic skyscraper, until tens of billions of transistors, each smaller than a virus, stand complete.

This explains why chips cost what they do, why one plant costs tens of billions of dollars, and why engineers obsess over dust: a single particle larger than a transistor can kill a chip worth hundreds of dollars. If you use electronics, you live downstream of a fab.

Key Concepts

• Ingot and wafer: Molten silicon is pulled into a single-crystal cylinder (Czochralski process), sliced into wafers and polished mirror-smooth; advanced fabs use 300 mm wafers.
• Doping: Trace impurities tune conductivity: phosphorus/arsenic add electrons (n-type), boron adds holes (p-type).
• Photolithography: The wafer is coated with photoresist, exposed to UV through a mask, and developed into a stencil. Extreme-UV tools use 13.5 nm light for the finest features.
• Etching: Wet (chemical) or dry plasma etching removes material through the stencil openings.
• Deposition: Oxidation grows SiO2 insulation; CVD adds nitride/polysilicon; sputtering lays metal.
• Ion implantation: Dopant atoms are fired into the silicon for precise depth control, then annealed.
• Metallization: A dozen-plus copper wiring layers connect everything, polished flat (CMP) between layers.
• Cleanroom and node: Air is filtered thousands of times cleaner than a hospital theater; "5 nm" is a generational label, not a literal size.

How It Works

1. Prep: A polished 300 mm wafer is aggressively cleaned.
2. Insulate: Heating in oxygen grows a thin silicon-dioxide film.
3. Pattern: Coat with photoresist, expose through the mask, develop into a stencil.
4. Etch or implant: Plasma-etch openings or shoot in dopants, then strip the resist.
5. Repeat: Every transistor and wiring layer gets its own cycle, hundreds of steps over months.
6. Wire up: Deposit copper interconnects layer by layer, polishing between them.
7. Test, cut, package: Probe every die, saw the wafer, discard failures, package the good chips.

Worked Example

How many chips fit on a 300 mm wafer? Radius 150 mm gives area 3.1416 x 150^2 = 70,686 sq mm. With 10 x 10 mm dies (100 sq mm): 70,686/100 = 707 sites. Edge waste (~15 percent) leaves about 600 whole dies; at 90 percent yield, about 540 working chips. This division is why fabs chase bigger wafers and smaller dies: every wasted square millimeter is money lost.

Common Misconceptions

• "A 5 nm chip has 5 nm transistors." Node names are marketing generations; real features are larger. What improved is density and efficiency.
• "Chips print in one shot." Dozens of separate exposures, each aligned to nanometers, build one chip over months.
• "A little dust is harmless." A dust speck dwarfs a transistor. Hence bunny suits and extreme air filtration.

Real-World Applications

• Processors and memory: Phone SoCs, CPUs and DRAM are flagship fab products.
• Sensors: Camera sensors, accelerometers and pressure sensors use specialized MEMS processes.
• Power devices: EV MOSFETs/IGBTs use thicker high-voltage processes.
• LEDs and photonics: Light emitters and data-center optical chips use the same tool family.

Fabrication is patient repetition: deposit, print with photolithography, etch or implant, repeat until billions of transistors and kilometers of copper wiring stand complete. Boron and phosphorus doping create the n and p regions; cleanrooms keep killer dust away; and the wafer math, ~540 good 10 mm chips per 300 mm wafer at 90 percent yield, sets the economics. Every device you own began as sand, purified, sliced and patterned by this process.