Sequential Circuits: SR, JK, D and T Flip-Flops Explained

Computers need memory: circuits that remember a 0 or 1 until told otherwise. Sequential circuits add feedback and a clock, so outputs depend on present inputs plus past history. The simplest one-bit memory element is the flip-flop.

Four classic types exist: SR, JK, D, and T, each with its own personality. With the clock dictating exactly when they update, flip-flops become registers, counters, and the state memory of every digital system. If gates are the muscles, flip-flops are the memory cells.

Key Concepts

• Latch vs flip-flop: a latch follows its input while enabled; a flip-flop updates only at a clock edge.
• SR: Set makes Q = 1, Reset makes Q = 0; S = 1, R = 1 together is forbidden.
• JK: fixes SR: J = 1, K = 1 toggles the output instead of being invalid. The most versatile type.
• D (data): Q copies D at each clock edge; a one-bit delay and the standard register block.
• T (toggle): T = 1 flips Q each clock edge; ideal for counters since each stage halves the frequency.
• Characteristic equation: formula for the next state from inputs and present state.
• Preset and clear: asynchronous inputs forcing Q to 1 or 0 immediately, used for power-on reset.
• Clock edge: the rising or falling instant triggering the flip-flop; input changes between edges are ignored.

Formulas

• SR: Qnext = S + R′·Q, with S·R = 0.
• JK: Qnext = J·Q′ + K′·Q; J = K = 1 gives Qnext = Q′ (toggle).
• D: Qnext = D. T: Qnext = T ⊕ Q.

Worked Example

A JK flip-flop starts at Q = 0 with J = K = 1. Trace three rising clock edges.

1. Edge 1: toggle, Q = 1. Edge 2: toggle, Q = 0. Edge 3: toggle, Q = 1.
2. The output flips every clock, running at half the clock frequency: exactly how binary counters divide frequencies.

Common Misconceptions

• The forbidden SR state destroys the flip-flop. Nothing is damaged; the outputs just become unpredictable. Forbidden means undefined, not dangerous.
• A flip-flop reacts instantly to input changes. Only latches do; edge-triggered flip-flops sample at the clock edge, which makes synchronous design reliable.
• Latch and flip-flop are the same thing. Their timing differs completely; confusing them causes race conditions.

Real-World Applications

• CPU registers are rows of D flip-flops holding data between operations.
• T/JK flip-flops build counters that divide frequencies and count events.
• State machines in vending machines and traffic lights store state in flip-flops.
• SR latches debounce mechanical switches into single clean pulses.

To recap: SR sets and resets with one forbidden combo, JK fixes it with toggle, D copies its input, T flips on command. Edge triggering updates them in lockstep with the clock, and from these one-bit memories grow registers, counters, and processors.