Pipelining and hazards
Computer Organization and Architecture · Engineering
CPU chip explorer
Interactive 3DLook inside a processor — data packets race between ALU, cache and control unit.
Controls
Drag the sliders or type a value — the simulation updates live.
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Study notes
Sequence: add r1,r2,r3 then sub r4,r1,r5. Without forwarding, sub's ID reads r1 before add's WB writes it: RAW hazard, 2 stall cycles. Forwarding routes add's EX/MEM result directly to sub's EX input: zero stalls. A branch mispredict similarly flushes fetched instructions: the pipeline's tax.