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CMOS Inverter: Operation and Characteristics For students.

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A CMOS inverter is the simplest CMOS logic gate: it takes a digital input and produces the opposite output, implementing the NOT function. It uses just two transistors — one PMOS on top connected to the supply voltage and one NMOS at the bottom connected to ground. Input high → NMOS conducts, output pulled low; input low → PMOS conducts, output pulled high.

It matters because the inverter is the atom of digital electronics. Every processor, memory chip and microcontroller is built from inverters and gates derived from them, and the CMOS construction is what makes modern chips fast while consuming almost no power when idle.

Key Concepts

  • MOSFET: a transistor switched by its gate voltage. NMOS conducts when its gate is high; PMOS conducts when its gate is low.
  • Pull-up / pull-down: the PMOS forms the path to VDD (supply); the NMOS forms the path to GND. Exactly one is on in steady state.
  • VTC (voltage transfer characteristic): the curve of output versus input voltage, showing the sharp transition between logic levels.
  • Logic thresholds: V_IL / V_IH bound valid low/high inputs; V_OL / V_OH bound the corresponding outputs.
  • Noise margins: NM_L = V_IL − V_OL and NM_H = V_OH − V_IH — how much noise the gate tolerates without misreading a bit.
  • Static vs dynamic power: in steady state almost no current flows, so static power is tiny; power is consumed mainly while switching capacitances.

Formulas

  • Dynamic power: P = α·C·V²·f, where α is the activity factor (fraction of cycles the output switches), C the load capacitance in farads, V the supply voltage in volts, f the clock frequency in hertz. P is in watts.
  • Noise margins: NM_L = V_IL − V_OL, NM_H = V_OH − V_IH, in volts.
  • Counts only switching power, ignoring leakage; the V² term is why lowering supply voltage saves the most energy.

Worked Example

Estimate dynamic power for C = 10 fF, VDD = 1.8 V, f = 1 GHz, activity factor α = 0.1.

  1. C = 10 × 10⁻¹⁵ F; f = 10⁹ Hz; V² = 3.24 V².
  2. P = 0.1 × (10 × 10⁻¹⁵) × 3.24 × 10⁹ = 0.1 × 3.24 × 10⁻⁵ = 3.24 × 10⁻⁶ W = 3.24 µW.

One inverter burns just 3.24 microwatts — negligible alone, but a billion switching gates make power the central design constraint. Halving the voltage would cut this roughly fourfold, thanks to V².

Common Misconceptions

  • "CMOS consumes zero power." Static power is near zero, but switching charges capacitances, and tiny transistors leak current when off.
  • "The PMOS connects to ground." Reversed: the PMOS pull-up always goes toward VDD, the NMOS pull-down toward GND.
  • "An inverter switches instantly." The output slews through intermediate voltages as capacitances charge — a real propagation delay that limits clock speed.

Real-World Applications

  • Logic design: NAND, NOR and complex gates combine inverter-like pull-up and pull-down networks.
  • Processors: billions of CMOS gates form CPUs, GPUs and microcontrollers.
  • Memory: SRAM cells and sense amplifiers rely on matched CMOS inverters.

The CMOS inverter pairs a PMOS pull-up with an NMOS pull-down so one is always off, giving near-zero standby power and full-swing outputs. Its switching energy, P = αCV²f, explains both why chips are fast and why power caps clock speeds.

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