Physical Design: Floorplanning Basics With easy examples.

Floorplanning is the stage of chip physical design where engineers decide the rough placement of big blocks, macros, memories and I/O on the silicon die before detailed placement begins. It answers the coarse questions: how big is the die, where do the large blocks sit, and where do the power rails run.

This matters because a bad floorplan can doom a chip: blocks far from their neighbours force long wires, long wires mean slow signals and extra power, and a die sized too small becomes unroutable while an oversized one wastes money. A good floorplan makes every later step, placement, clock-tree synthesis and routing, dramatically easier.

Key Concepts

• Die and core area: the die is the full chip; the core is the region inside the I/O ring where logic lives.
• Macros: large pre-built blocks such as SRAMs, PLLs and analog IP placed as rigid rectangles.
• Utilization: the fraction of core area occupied by cells; higher means a smaller cheaper die but harder routing.
• Aspect ratio: the die's height-to-width ratio; square is typical.
• Pin assignment: placing each block's pins so wires between blocks stay short and uncrossed.
• Routing channels: gaps between macros for wires to pass; too narrow means congestion.
• Power grid: the mesh of wide metal straps delivering supply voltage, planned early since it competes for routing space.

How It Works

1. Import the netlist: read the synthesized logic and macro sizes.
2. Size the die: add cell area at target utilization plus macro area, then choose dimensions.
3. Place macros: put large memories and IP first, usually along edges, pins facing their heaviest data partners.
4. Assign pins, plan channels: arrange pins to minimize crossings and reserve routing channels.
5. Plan the power grid: lay out the supply mesh and verify voltage drop stays within limits.
6. Estimate and iterate: trial place-and-route checks timing and congestion, then adjust.

Worked Example

Standard cells need 8 mm² at 100 percent density with target utilization 80 percent, so cells need 8/0.8 = 10 mm² of core. SRAM macros add 4 mm². Total core = 14 mm², and a square core has side √14 ≈ 3.74 mm.

Add a 0.5 mm I/O ring on each side for pads and power: die side becomes 3.74 + 2 × 0.5 = 4.74 mm, die area about 22.5 mm². If trial routing reports central congestion, the engineer widens a channel by shifting two macros, growing the die slightly. Trading a little area for routability is the daily currency of floorplanning.

Common Misconceptions

• Floorplanning equals placement. Floorplanning is coarse, positioning big blocks and sizing the die; placement later puts millions of individual cells.
• A smaller die is always cheaper. An over-shrunk die congests, fails timing and may need extra metal layers costing more than the saved silicon.
• Macros can go anywhere. Each macro's pins must face data partners with routing channels left open; a careless memory can block half the chip's wiring.

Real-World Applications

• Smartphone SoC floorplans balance CPU, GPU, modem and memory macros against thermals and wire length.
• 3D-stacked chips extend floorplanning vertically, aligning through-silicon vias between dies.
• Chip cost estimation starts from floorplan area: die size plus yield math sets the price per chip.

Floorplanning is chip-scale urban planning: zone the big districts first, leave room for roads and power, and the millions of tiny cells practically place themselves.