Chip Fabrication Basics: Complete Beginner's Guide

Chip fabrication builds billions of transistors onto a thin slice of silicon called a wafer. It works layer by layer: each layer adds patterned material, and a stack of 10 to 15 patterned layers eventually becomes a working processor or memory chip.

Every electronic device exists only thanks to this process. The two critical patterning steps are lithography, which draws microscopic circuit patterns with light, and etching, which carves them into the silicon. Together they set how small transistors can be, and transistor size has driven fifty years of computing progress.

Key Concepts

• Wafer: a disc of ultra-pure single-crystal silicon, typically 300 mm across, on which hundreds of chips are built simultaneously.
• Photoresist: light-sensitive coating; light changes its solubility so exposed regions wash away, leaving a stencil.
• Photomask / reticle: the glass plate carrying one layer's circuit pattern, projected onto the wafer.
• Lithography: projecting the mask pattern with ultraviolet light; leading fabs use extreme ultraviolet (EUV) at 13.5 nm wavelength.
• Etching: removing material where the stencil is open. Wet etching uses liquid chemicals (undercuts sideways); dry/plasma etching uses ionized gas (vertical walls).
• Doping: implanting atoms like boron or phosphorus to create the p-type and n-type regions forming transistors.
• Cleanroom: the dust-free factory; one dust particle is gigantic next to a transistor and can ruin a chip.

Formulas

• Resolution (Rayleigh): smallest feature ≈ k1·λ/NA, with λ the wavelength, NA the lens numerical aperture, k1 near 0.3.
• Poisson yield: Y = e^(−A·D), where A is die area and D defect density; estimates the fraction of good dies.
• Dies per wafer: roughly (π·(d/2)²)/A minus edge losses, with d the wafer diameter.
• Assumption: defects are random and independent; systematic process drift is not captured by the simple model.

Worked Example

A chip with die area A = 1.2 cm² is built on 300 mm wafers at defect density D = 0.4 defects/cm². Yield Y = e^(−1.2·0.4) = e^(−0.48) ≈ 0.619, so about 61.9 percent of dies work. Wafer area is π·15² ≈ 706.9 cm², giving about 706.9/1.2 ≈ 589 candidate dies, of which 589 × 0.619 ≈ 364 are good.

Shrink the design to 0.6 cm² at the same defect density: Y = e^(−0.24) ≈ 0.787, the wafer holds about 1,178 dies, yielding roughly 927 good chips. Smaller chips are dramatically cheaper: more dies per wafer AND each die more likely to dodge defects. Yield math is the economic engine behind Moore's law.

Common Misconceptions

• Smaller transistors are better in every way. They are faster and denser, but leakage and power density worsen, which is why clock speeds stalled around 2005.
• Lithography prints ink like a printer. No ink is involved; light only patterns the stencil, and deposition plus etching add or remove material.
• One wafer makes one chip. A 300 mm wafer carries hundreds of dies built in parallel, separated only at the end.

Real-World Applications

• Every CPU, GPU and memory chip in phones and computers uses this lithography-plus-etching flow.
• Image sensors and MEMS microphones use specialized etches to carve 3D microstructures.
• Power transistors for electric vehicles use thicker layers and deep etches on the same toolset.

Lithography draws the pattern, etching carves it, and a dozen cycles build a complete chip. The yield equation carries the business logic: low defects plus small dies make silicon the cheapest high technology ever made.